Nonvolatile memory devices such as flash memory devices are well known in the art. Typically, a nonvolatile flash memory device is arranged in a plurality of blocks, with each block having a plurality of nonvolatile memory cells arranged in a plurality of rows and columns. In operation, a block of memory cells are erased together, simultaneously. In programming, selective memory cells of a block are programmed. All of the cells of a flash memory device must be erased before they can be programmed. Thus, as the data of memory cells of a block become “stale,” the replacement data is programmed into memory cells in other blocks. Once all the memory cells in a certain block are “used” or “stale,” then all the memory cells of that block are erased, simultaneously. However, typically, the operations of programming and erasing are not done simultaneously.
In the prior art, various disclosures have been made with regard to expediting the erasure of a block. See, for example, U.S. Pat. Nos. 6,571,312; 6,567,307; 5,553,261; 5,602,987; and 5,818,761. In U.S. Pat. No. 6,081,450, disclosure is made to a non-volatile semiconductor memory device in which write and erase operations can occur simultaneously in different array blocks. However, in that reference, two row decoders are used necessitating extra space on the integrated memory cell. Finally, the use of global bit lines connected to local bit lines is also disclosed. See, for example, U.S. Pat. No. 5,818,761, FIG. 10. However, this is not used to provide for simultaneous program and erase function in the same array.
Accordingly, it is one object of the present invention to improve the performance of a nonvolatile flash memory device.